A Novel FPGA Architecture using Memristor-Transistor Hybrid Approach

This work focuses on the design of a novel FPGA architecture based on memristor-transistor hybrid approach. A lot of research has been carried out in the field of FPGA that has focused on decreasing the size and power consumption of FPGAs. However, still FPGAs are larger in area, slower in speed and more power consuming. In this work, basic building blocks like MUX, NOR gate, D flip flop, NOT gate and buffer are designed and implemented using memristor-transistor hybrid approach. These basic building blocks are combined to form Configurable Logic Blocks (CLBs), Switch Boxes (SBs) and Connection Boxes (CBs) of FPGA. Proposed hybrid basic building blocks of FPGA are smaller in size and lower in power consumption as compared to the conventional transistor-only building blocks. For experimental purpose, first we compare the area and power of conventional and proposed basic building blocks and achieve the average area and power efficiency of 30% and 60% respectively. Similarly, the area gain of a 2 input single tile based on proposed basic building block is 39%. Then, we also explore the overall area of memristortransistor hybrid FPGA architecture for sixteen largest MCNC benchmarks and present the results.